View EK42452-01_8398879.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

document no. doc-14014-3 www.psemi.com page 1 of 11 ?2013-2014 peregrine semiconductor corp. all rights reserved. rf2 rf5 rf4 cmos control/ driver and esd v1 v2 esd rf1 v3 rf3 esd 50 esd 50 esd 50 esd 50 esd 50 rfc vss ext (optional) v dd figure 1. functional diagram figure 2. package type 24-lead 4x4 mm qfn product specification ultracmos ? sp5t rf switch 450?4000 mhz pe42452 features ?? five symmetric, absorptive rf ports ?? high isolation ?? 61 db @ 900 mhz ?? 55 db @ 2100 mhz ?? 52 db @ 2700 mhz ?? 44 db @ 4000 mhz ?? high linearity ?? iip2 of 96 dbm ?? iip3 of 57 dbm ?? 1.8v control logic compatible ?? 105c operating temperature ?? fast switching time of 265 ns ?? three pin cmos logic control ?? external negative supply option ?? esd performance ?? 4kv hbm on rf pins to gnd ?? 1.5kv hbm on all pins product description the pe42452 is a harp? technology-enhanced absorptive sp5t rf switch designed for use in 3g/4g wireless infrastructure and other high performance rf applications. this switch is a pin-compatible upgraded version of the pe42451 with 1.8v control logic. it is comprised of five symmetric rf ports and has very high isolation. an integrated cmos decoder facilitates a three-pin low voltage cmos control interface and an external negative supply option. in addition, no external blocking capacitors are required if 0v dc is present on the rf ports. the pe42452 is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on- insulator (soi) technology on a sapphire substrate. peregrine?s harp? technology enhancements deliver high linearity and excellent harmonics performance. it is an innovative feature of the ultracmos ? process, offering the performance of gaas with the economy and integration of conventional cmos. doc-02114
product specification pe42452 page 2 of 11 ?2013-2014 peregrine semiconductor corp. all rights reserved. document no. doc-14014-3 ultracmos ? rfic solutions table 1. electrical specifications @ 25c (z s = z l = 50? ) unless otherwise noted normal mode 1 : v dd = 3.3v, vss ext = 0v or bypass mode 2 : v dd = 3.3v, vss ext = -3.3v notes: 1. normal mode: single external positive supply used 2. bypass mode: both external positive supply and external negative supply used 3. the input 0.1 db compression point is a linearity figure of merit. refer to table 3 for the operating rf input power (50 ? ) parameter path condition min typ max unit operating frequency 450 4000 mhz insertion loss rfc?rfx 450 mhz?900 mhz 900 mhz?2100 mhz 2100 mhz?2700 mhz 2700 mhz?4000 mhz 0.95 1.15 1.30 1.60 1.15 1.35 1.55 1.90 db db db db isolation rfc?rfx 450 mhz?900 mhz 900 mhz?2100 mhz 2100 mhz?2700 mhz 2700 mhz?4000 mhz 56 52 49 41 61 55 52 44 db db db db return loss (active port) rfx 450?4000 mhz 16 db return loss (terminated port) rfx 450?4000 mhz 23 db input 0.1 db compression point 3 rfc?rfx 1950 mhz 35 dbm input ip2 rfc?rfx 1950 mhz 96 dbm input ip3 rfc?rfx 1950 mhz 57 dbm switching time 50% control to 10% or 90% rf 265 345 ns isolation rfx?rfx 450 mhz?900 mhz 900 mhz?2100 mhz 2100 mhz?2700 mhz 2700 mhz?4000 mhz 56 51 49 41 60 53 52 42 db db db db
product specification pe42452 page 3 of 11 document no. doc-14014-3 www.psemi.com ?2013-2014 peregrine semiconductor corp. all rights reserved. table 2. pin descriptions gnd rfc gnd gnd vss ext 24 23 22 21 20 19 v3 gnd rf3 gnd gnd rf2 gnd 7 8 9 10 11 12 figure 3. pin configuration (top view) notes: 1. rf pins 2, 5, 8, 11, 14, and 22 must be at 0v dc. the rf pins do not require dc blocking capacitors for proper operation if the 0v dc requirement is met 2. use vss ext (pin 20, refer to table 3 ) to bypass and disable internal negative voltage generator. connect vss ext (pin 20, vss ext = gnd) to enable internal negative voltage generator pin # name description 1, 3, 4, 6, 7, 9, 10, 12, 13, 15, 21, 23, 24 gnd ground 5 rf4 1 rf port 4 8 rf3 1 rf port 3 11 rf2 1 rf port 2 14 rf1 1 rf port 1 16 v dd supply voltage 17 v1 digital control logic input 1 18 v2 digital control logic input 2 19 v3 digital control logic input 3 20 vss ext 2 external vss negative voltage control/ ground 22 rfc 1 rf common pad gnd exposed pad: ground for proper operation 2 rf5 1 rf port 5 table 3. operating ranges parameter symbol min typ max unit normal mode 1 supply voltage v dd 2.3 5.5 v supply current i dd 110 a bypass mode 2 supply current i dd 50 a negative supply voltage vss ext -3.6 -3.2 v normal or bypass mode digital input high (v1, v2, v3) v ih 1.17 3.6 v digital input low (v1, v2, v3) v il -0.3 0.6 v digital input current 3 i ctrl 1 a rf input power, cw p max,cw 33 dbm rf input power into terminated ports, cw p max,term 24 dbm operating temperature range t op -40 +105 c supply voltage v dd 2.7 5.5 v notes: 1. normal mode: connect pin 20 to gnd to enable internal negative voltage generator 2. bypass mode: apply a negative voltage to vss ext (pin 20) to bypass and disable internal negative voltage generator 3. the pull-down resistor in the evk schematic may increase control current table 4. absolute maximum ratings exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. parameter/condition symbol min max unit supply voltage v dd -0.3 5.5 v voltage on any dc input v i -0.3 3.6 v maximum input power p max,abs 34 dbm storage temperature range t st -60 +150 c esd voltage hbm 1 all pins rf pins to ground v esd,hbm 1500 4000 v v esd voltage mm 2 , all pins v esd,mm 100 v esd voltage cdm 3 , all pins v esd,cdm 500 v notes: 1. human body model (mil_std 883 method 3015) 2. machine model (jedec jesd22-a115) 3. charged device model ( jedec jesd22-c101d)
product specification pe42452 page 4 of 11 ?2013-2014 peregrine semiconductor corp. all rights reserved. document no. doc-14014-3 ultracmos ? rfic solutions electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. latch-up avoidance unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. mode v3 v2 v1 all off 0 0 0 rf1 on 0 0 1 rf2 on 0 1 0 rf3 on 0 1 1 rf4 on 1 0 0 rf5 on 1 0 1 all off 1 1 0 unsupported 1 1 1 table 5. truth table moisture sensitivity level the moisture sensitivity level rating for the pe42452 in the 24-lead 4x4 qfn package is msl1. switching frequency the pe42452 has a maximum 25 khz switching rate in normal mode (pin 20 = gnd). a faster switching rate is available in bypass mode (pin 20 = vss ext ). the rate at which the pe42452 can be switched is then limited to the switching time as specified in table 1. switching frequency describes the time duration between switching events. switching time is the time duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. optional external vss control (vssext) for applications the require a faster switching rate or spur-free performance, this part can be operated in bypass mode. bypass mode requires an external negative voltage in addition to an external v dd supply voltage. as specified in table 3 , the external negative voltage (vss ext ) when applied to pin 20 will disable and bypass the internal negative voltage generator. spurious performance the typical low-frequency spurious performance of the pe42452 in normal mode is ?120 dbm (pin 20 = gnd). if spur-free performance is desired, the internal negative voltage generator can be disabled by applying a negative voltage to vss ext (pin 20). note: logic state 111 is unsupported and should not be used under any operating conditions
product specification pe42452 page 5 of 11 document no. doc-14014-3 www.psemi.com ?2013-2014 peregrine semiconductor corp. all rights reserved. typical performance data @ 25c and v dd = 3.3v unless otherwise noted figure 5. insertion loss vs temp (rfc?rfx) figure 6. insertion loss vs v dd (rfc?rfx) figure 4. insertion loss (all paths)
product specification pe42452 page 6 of 11 ?2013-2014 peregrine semiconductor corp. all rights reserved. document no. doc-14014-3 ultracmos ? rfic solutions figure 7. isolation vs temp (rfc?rfx) figure 8. isolation vs v dd (rfc?rfx) figure 9. isolation vs temp (rfx?rfx) typical performance data @ 25c and v dd = 3.3v unless otherwise noted figure 10. isolation vs v dd (rfx?rfx)
product specification pe42452 page 7 of 11 document no. doc-14014-3 www.psemi.com ?2013-2014 peregrine semiconductor corp. all rights reserved. 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 00.511.522.533.544.5 iip3 (dbm) frequency (ghz) rf1 rf2 rf3 rf4 rf5 figure 11. active port return loss vs temp figure 12. active port return loss vs v dd figure 13. rfc port return loss vs temp typical performance data @ 25c and v dd = 3.3v unless otherwise noted figure 14. rfc port return loss vs v dd figure 15. return loss (all ports terminated) figure 16. iip3 vs frequency
product specification pe42452 page 8 of 11 ?2013-2014 peregrine semiconductor corp. all rights reserved. document no. doc-14014-3 ultracmos ? rfic solutions evaluation kit the sp5t switch evaluation board was designed to ease customer evaluation of peregrine?s pe42452. the rf common port is connected through a 50 ? transmission line via the top sma connector. rf1, rf2, rf3, rf4 and rf5 are connected through 50 ? transmission lines via side sma connectors. a through 50 ? transmission is available via sma connectors rfcal1 and rfcal2. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the evk board is constructed with four metal layers on dielectric materials of rogers 4003c and 4450 with a total thickness of 32 mils. layer 1 and layer 3 provide ground for the 50 ? transmission lines. the 50 ? transmission lines are designed in layer 2 for high isolation purpose and use a stripline waveguide design with a trace width of 9.4 mils and trace metal thickness of 1.8 mils. the board stack up for 50 ohm transmission lines has 8 mil thickness of rogers 4003c between layer 1 and layer 2, and 10 mil thickness of rogers 4450 between layer 2 and layer 3. please consult manufacturer's guidelines for proper board material properties in your application. the pcb should be designed in such a way that rf transmission lines and sensitive dc i/o traces such as vss ext are heavily isolated from one another, otherwise the true performance of the pe42452 will not be yielded. figure 17. evaluation board layout prt-29105
product specification pe42452 page 9 of 11 document no. doc-14014-3 www.psemi.com ?2013-2014 peregrine semiconductor corp. all rights reserved. figure 18. evaluation board schematic doc-14027
product specification pe42452 page 10 of 11 ?2013-2014 peregrine semiconductor corp. all rights reserved. document no. doc-14014-3 ultracmos ? rfic solutions figure 19. package drawing ? 24-lead 4x4 mm qfn doc-58197 figure 20. marking specifications 42452 yyww zzzzz doc-51207 = pin 1 designator yyww = date code zzzzz = las five digits of the lot number
product specification pe42452 page 11 of 11 document no. doc-14014-3 www.psemi.com ?2013-2014 peregrine semiconductor corp. all rights reserved. figure 21. tape and reel drawing device orientation in tape top of device pin 1 tape feed direction a 0 = 4.35 b 0 = 4.35 k 0 = 1.1 table 6. ordering information pe42452a-z pe42452 sp5t rf switch green 24-lead 4x4 mm qfn 3000 units/t&r EK42452-01 pe42452 evaluation kit evaluation kit 1/box ordering code description package shipping method advance information: the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregr ine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information for sales and contact information please visit www.psemi.com .

▲Up To Search▲

Price & Availability of EK42452-01

	To Download EK42452-01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .